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Xilinx – Hyderabad, Andhra Pradesh – Job Title: STAFF DESIGN ENGINEER – Physical Design and STA Lead – 150961 Primary Location India-India-Hyderabad Job: Design Engineering Schedule: Full-time Description Xilinx is the world’s leading provider of All Programmable FPGAs, SoCs and 3D ICs. These industry-leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. Our All Programmable devices underpin today’s most advanced electronics. Among the broad range of end markets we serve are: Aerospace/Defense Automotive Broadcast Consumer High Performance Computing Industrial / Scientific / Medical (ISM) Wired Wireless Job Description: As the Physical design lead of the MPSoC design team in Hyderabad, you’ll be responsible for leading physical design closure efforts for complex designs. Taking design from RTL to GDSII. Owning and driving few aspects of design like synthesis, DFT , timing and physical design. Essential Duties , Competencies & Responsibilities include, but not limited to: Leading a team to take a design from RTL to GDSII Hands on ownership of one or more activities — physical implementation , DFT , timing Interacting with RTL design teams to resolve all implementation issues Participate in design reviews and design closure discussions Develop or enhance scripts for various physical closure activities Provides technical mentoring, and knowledge sharing via brown bags, formal presentations, and working meetings to broad organization and leaders Defines and drives workflow processes to mitigate challenges and support planning Job Requirements: Good understanding of complete physical design flow. Must have gone through multiple tapeout cycles, revisions and metal ECOs Expertise with PD,STA tools (like ICC, Primetime) is a must Relevant Course work, research, professional experience on physical closure, floorplan, CTS, routing, timing, noise, crosstalk, electro migration, IR drop, process variations, characterization, 3D ICs, low power cmos, digital logic and circuit design, ASIC/ SOC integration. Strong scripting skills using Perl, TCL, C-shell, Make and/or other scripting languages. Timing characterization and post silicon timing correlation experience a plus. Experience/ project work on critical path simulation, clock path simulation (jitter/duty cycle) with Spice a plus Strong verbal and written communication skills. Qualifications Enter Education Requirements : MSEE Enter Years of Experience 10 #H#… – Permanent – Full-time
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STAFF DESIGN ENGINEER - Physical Design and STA Lead
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